High Frequency Characterization and Modeling of VLSI On-Chip Interconnects
نویسندگان
چکیده
| Modeling of on-chip inductance for chips with realistic power/ground wires and grids is presented. Analytical formulae as well as eld solvers are used to analyze inductance of on-chip structures including power/ground grids, ground plane and substrate e ects. Insights and design guidelines to reduce wire inductance are demonstrated. An accurate capacitance modeling approach is also presented.
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